FIG. 1 illustrates a prior art slew rate controlled output buffer 100 with a feedback capacitor CF between the nodes Vo and Vf. Node Vo represents an external input-output (I/O) pad, where CL is the load capacitance on the node Vo. Transistors P1 and N1 represent a driver of the output buffer 100. Transistors P3, N3 and P2, N2 represent pre-drivers to the driver transistors P1 and N1, respectively, and drive an input signal Vi to the driver. Transistors P4 and N4 are part of the feedback network that theoretically allow the slew rate of the buffer at node Vo to depend on the feedback capacitor CF and the switch current generated by transistors P1 and N1. The term “transistors” and “devices” herein are interchangeably used.
The term “slew rate” herein refers to rise and fall times of signals at the node Vo measured from voltage points 10-20% (for example) above the low signal level and voltage points 10-20% (for example) below the high signal level of the signal on node Vo.
However, the slew rate controlled output buffer 100 of FIG. 1 suffers from transistor reliability issues for transistors P4 and N4, where the reliability issues are caused by an overshoot of voltage on the node Vf. For example, consider an operating condition of the buffer 100 when the node Vf is initially at its highest possible voltage of Vcc-Vtp, where Vcc is the power supply level and where Vtp is the threshold voltage of transistor P4. Continuing with the same example, consider that the output buffer receive mode, i.e. transistors P4, N4, P1, and N1, are all off. Due to electric coupling across nodes of the feedback capacitor CF, the node Vf will charge up as the pad voltage on the node Vo switches/transitions. As the node Vf charges up, the transistor P4 will eventually turn on and cause the node Vf to stabilize to a Vcc+|Vtp| level. When the node Vf is charging up and the node Vo (also referred to as the pad) switches from a logical low level to a logical high level, the node Vf will experience a strong coupling from the pad causing an overshoot voltage on node Vf to be much higher than Vcc+|Vtp| level.
This overshoot voltage causes electrical overstress on devices P4 and N4, thus aging those devices faster than other devices of the buffer 100. The overshoot voltage may also be caused by any mismatch in the number of transistors of P1 and N1 turned on. These overshoots will eventually cause the buffer to malfunction because the devices P4 and N4 will be damaged by the overshoots on node Vf. The overshoot on node Vf further causes duty cycle uncertainty on the first signal transition during transmit mode of the buffer 100.